1. Field of the Invention
This invention relates to a scan driver of liquid crystal display (LCD), and particularly relates to a scan driver of liquid crystal display with fault detection and correction function.
2. Description of the Prior Art
In fabricating LCD (Liquid Crystal Display) panel, the TFT (Thin Film Transistor) are frequently utilized, and the LTPS (Low Temperature Polycrystalline Silicon) technology is employed to fabricate the TFT in the lately technology. Usually, in the LTPS process, the scan driver is fabricated on the glass substrate, on which the, TFT LCD is fabricated. However, the yield of the processes fabricating the scan driver is not stable, so the redundant scan driver shift register is necessary for the LCD. The fault detection and correction circuit of the shift register of the scan driver mentioned above is used to avoid the scan driver failure due to any failure of scan driver shift register.
In the prior art, all the fault detection and correction circuits are fabricated on a single side of a glass substrate. In other words, the scan driver on the glass substrate is fabricated on a single side (left or right). Even though the scan drivers are fabricated on both sides (left and right) of the glass substrate in a temp to simultaneously drive the gate buses of the TFT array, the prior art still can not drive the gate buses simultaneously from both sides. The purpose of the present invention is to propose the circuit for fault detection and correction such that the gate buses can be driven from a single side or simultaneously from both sides of the transparent (such as glass) substrate.
In the traditional TFT LCD, the mobility of the carrier in the amorphous silicon utilized to fabricate the TFT on the panel is lower than that in the crystal silicon utilized in the normal semiconductor device. So the process utilizing amorphous silicon can be used to fabricate the thin film transistor (TFT) on the panel as switches only. The process mentioned above can not be used to fabricate the transistor in the data driver or the scan driver. Thus, the scan driver and the data driver can only be fabricated in the integrated circuit using silicon as substrate instead of using glass panel. The configuration of the TFT LCD is shown in FIG. 1, in which the panel 10 is made of glass, and the TFT array is fabricated on the panel 10. The scan driver integrated circuit 11 and the data driver integrated circuit 12 are both utilized to drive the transistor in the TFT array. The TFT array mentioned above includes many transistors (TFT) 14, each connecting a transparent electrode 16. In the prior art shown in FIG. 1, since the scan driver 11 and the data driver 12 are fabricated on the substrate other than the glass substrate, they must be attached to the panel 10. The assembly takes additional effort and costs.
As the technology proceeds, the low temperature polycrystalline silicon (LTPS) technology is developed to fabricate the TFT LCD, and the polycrystalline silicon can be used to fabricate the transistors for not only switches in pixels but also scan driver circuit as well as in the data driver circuit. In other words, by using the LTPS technology, the scan driver and the data driver can be fabricated on the same panel (glass substrate) of the LCD such that the cost of the LCD is reduced. The configuration of the LCD mentioned above is shown as FIG. 2, in which the panel 20 is made of glass, and the TFT array is fabricated on the panel 20. The scan driver 21 and the data driver 22 are utilized to drive the TFT array. The TFT array mentioned above includes many transistors (TFT) 24, each connecting a transparent electrode 26. In the prior art shown in FIG. 2, the scan driver 21 and the data driver 22 are fabricated on the panel (glass substrate) 20. As shown in FIG. 2, the scan driver 21 is at one side of the panel 20 and is used to sequentially drive each gate bus connecting to the gate of each thin film transistor. Because only one set of scan driver is provided on the panel, any fault on the scan driver may degrade the panel and affect the yield rate.
In order to literally utilize the fault detection and correction circuit in the scan driver, and to rapidly drive the gate buses on the panel, a configuration with scan driver at both sides of the panel is provided. As shown in FIG. 3, the TFT array is fabricated on the panel 30, which is made of glass. The scan driver integrated circuit 31 and the data driver integrated circuit 32 are both utilized to drive the transistors in the TFT array. The TFT array mentioned above includes many transistors (TFT) 34, each connecting a transparent electrode 36. In the prior art shown in FIG. 3, the scan driver integrated circuit 31 and the data driver integrated circuit 32 are fabricated on the panel (glass substrate) 30, and the scan driver 31 is fabricated on both sides of the panel (glass substrate) 30. Because the scan driver 31 at both sides of the panel can drive the gate bus, it is easier to drive the transistors on each gate bus.
The circuit diagram of the scan driver shown in FIG. 1, FIG. 2, and FIG. 3 is a traditional one that composed of serial connected D-type flip flops (D-type FF:DFF), which is shown in FIG. 4A. The input terminal IN is coupled to the first D-type FF Q1, in addition, the terminal CK provides the clock pulse to the first D-type FF Q1, the second D-type FF Q2, and third D-type FF Q3 . . . etc. The waveform of the signal on the input terminal IN, the terminal CK, the output of the first D-type FF Q1, the second D-type FF Q2, and the third D-type FF Q3 are shown in FIG. 4B. Because of the pulse on each output terminal of the shift registers, all the transistors (TFT) on the scan bus are activated (on).
When the LTPS process is utilized to fabricate the shift register of the scan driver integrated circuit, the resulted shift register often fail, and thus the stuck-at-zero fault or the stuck-atone fault of the output of the shift register is frequently resulted. To solve this problem, three identical shift registers are fabricated instead of one shift register, and the majority of the output of the three identical shift registers is taken to represent the output of all the shift registers. The other method employed to solve the foregoing issue is to utilize laser to cut off and thus block the failed region. This is usually used in the one-side-driving-model LCD, i.e., the scan driver fabricated on only one side of the panel of the LCD, such as that shown in FIG. 2.
At the beginning of developing LCD manufacturing technology, in order to overcome the issue of low yield, usually, an xe2x80x9cORxe2x80x9d gate is connected to three sets of serial connected D-type FFs. The OR gate mentioned above is used to transmit the correct signal to the following sets of serial connected D-type FFs. As shown in FIG. 5A, it is clear that when a stuck-at-zero fault happened in any set of the serial connected D-type FFs, the correct signal (logic one or logic zero) can be transmitted to the following sets of serial connected D-type FFs, even there is only one set of serial connected D-type FF works properly. On the other hand, when there is a stuck-at-one fault happened in a set of the serial connected D-type FFs, the output of the OR gate 40 will stuck at logic one too. When the phenomenon happened, an detection is made through the test pad to find out which output(s) of the set of the serial connected D-type FFs is stuck at logic one. After finding which set of serial connected D-type FFs is stuck at one, e.g., the set of serial connected D-type FFs 41 is stuck at one, laser is utilized to cut off the output of the set of serial connected D-type FFs 41. For example, the laser can focus at point P1 to cut off the set of serial connected D-type FFs 41. So the input of the OR gate 40 which stuck at logic one is prevent from connecting to the OR gate 40, and the xe2x80x9cfloatingxe2x80x9d phenomenon will not happen because each input terminal of the OR gate 40 is coupled to ground through a resistor. However, it is impossible to fabricate test pad between each two DFFs because the test cost will terribly increase. If the prior art scan driver with redundancy function have the structure shown in FIG. 5A, the disadvantages are described above.
Besides, to avoid the LCD become. useless due to one shift register fail, the prior art proposed a circuit without using test pad and laser. The circuit diagram of the circuit mentioned above is shown in FIG. 5B, which is similar to that shown in FIG. 5A. According to the circuit diagram shown in FIG. 5B, the majority-dominating circuit 49 is placed between each two neighboring stage of DFFs to replace the test pad and the grounding resistors. Besides, when any fault happened in the shift register, it is unnecessary to use laser to cut off the shift register because of the majority-dominating circuit 49. According to FIG. 5B, if the majority of the points A, B, and C have logic zero, the output of the majority-dominating circuit 49 is at the level of logic zero. On the contrary, if the majority of the points A, B, and C have logic one, the output of the majority-dominating circuit 49 is at the level. of logic one. Even one DFF break down, the majority-dominating circuit 49 can output correct signal to the next stage of DFF.
The two types of prior art shift register mentioned above are based on one-side-driving consideration. As for the two-side-driving configuration shown in FIG. 3, once the shift register at one side fails, that is, it""s output is different from the corresponding one across the panel, the voltage on the gate buses being following the failed stage will vary from one side to the other, also causing DC current flowing through the scan lines, and making this panel unacceptable.
A driving apparatus of a LCD (Liquid Crystal Display) with fault detection and correction function is proposed by the present invention. So the scan driver according to the present invention can drive the scan line either from one side or from both sides of the scan line. The driving apparatus according to the present invention includes the following elements.
The first driving device is used to transmit signal from the previous stage through the present stage to the next stage. Also, the second driving device is used to transmit signal from the previous stage through the present stage to the next stage. The plurality of scan buses couples the first driving device and the second driving device of a same stage, and each of the first driving device and the second driving device includes a plurality of D-type flip flops (DFF) and a plurality of fault detection and correction circuits in the present invention. The input terminals of each of the plurality of fault detection and correction circuits is coupled to output terminal of one of the plurality of DFFs at previous stage and is coupled to output terminal of one of the plurality of DFFs at present stage. Each of the output terminal of each of the plurality of fault detection and correction circuits is coupled to one bus of the plurality of scan buses and one of the plurality of DFFs at next stage. The fault detection and correction circuit is utilized to determine whether transmit signal from a first Delay type Flip Flop (DFF) at present stage into input terminal of a second DFF at next stage, or transmit signal from a third DFF at present stage through a scan bus into the second DFF.
The fault detection and correction circuit of the driving apparatus according to the present invention includes the following elements. The first detecting device generates a first logic level at output terminal of the first detecting device responding to a stuck-at-zero fault happened in the first DFF. The first DFF, the second DFF, the third DFF, and the scan bus is formed on a silicon substrate or on a transparent substrate such as glass. The output terminal of a fourth DFF at previous stage is coupled to the input terminal of the first detecting device.
The second detecting device generates the first logic level at output terminal of the second detecting device responding to a stuck-at-one fault happened in the first DFF. The control signal generating device generates a first control signal when all input terminals of the control signal generating device exhibiting a second logic level. The control signal generating device generates a second control signal when one of input terminals of the control signal generating device exhibiting the first logic level, the output terminals of the first detecting device and the second detecting device is coupled to input terminals of the control signal generating device.
The transmission control device transmits signal from the first DFF to the second DFF and the scan bus responding to the first control signal. The transmission control device cuts off electrical coupling between the first DFF and the second DFF as well as the scan bus responding to the second control signal, and then signal from the third DFF is transmitted through the scan bus to the second DFF. One side of the scan bus is electrically coupled to the first DFF locating at one side of the transparent substrate, the other side of the scan bus is electrically coupled to the second DFF locating at the other side of the transparent substrate. The stuck-at-zero fault is defined as-output terminal of the first DFF keeping at the first logic level when output terminal of the fourth DFF at previous stage changing from the logic one (logic high) to the logic zero level (logic low). In conclusion, when the output of a DFF is permanently equal to logic zero no matter what the input is, the DFF is defined as having the stuck-at-zero fault. The stuck-at-one fault is defined as output terminal of the first DFF keeping at the second logic level when all output terminals of all the DFFs changing from logic one (logic high) to logic zero (logic low). In conclusion, when the output of a DFF is permanently equal to logic one no matter what the input is, the DFF is defined as having the stuck-at-one fault. The activity of a plurality of thin film transistors is controlled by the signal on the scan bus, which electrically coupled to the gates of the plurality of TFTs. In addition, the electricity of the plurality of thin film transistors controls the orientation of polarity of molecule of liquid crystal placed over the transparent substrate.
The first detecting device, the second detecting device, the control signal generating device, and the transmission control device is fabricated by a LTPS (Low Temperature Polycrystalline Silicon) technology. The first detecting device in one preferred embodiment of the present invention includes a first NAND gate, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first inverter, a second inverter, and a first NAND gate. The second detecting device in one preferred embodiment of the present invention includes a sixth transistor, a seventh transistor, and a second NAND gate.
The control signal generating device in one preferred embodiment of the present invention including a third NAND gate and a third inverter. The output terminals of the control signal generating device are coupled to the transmission control device to provide the first control signal and the second control signal to the transmission control device. In addition, each of the first control signal and the second control signal includes a logic high level and a logic low level. The transmission control device according to the present invention is a transmission gate including a CMOS (Complementary Metal Oxide Semiconductor Field Effect Transistor) transmission gate having a first control gate, a second control gate, an input terminal, and an output terminal. Either the first control signal or the second control signal is coupled to the first control gate and the second control gate at a time.
The CMOS transmission gate is conductive between the input terminal and the output terminal when the first control signal is coupled to the first control gate and the second control gate. The CMOS transmission gate is insulating between the input terminal and the output terminal when the second control signal is coupled to the first control gate and the second control gate. The first logic level in one preferred embodiment of the present invention is a logic low level, and the second logic level is a logic high level.